Integrated Circuits (ICs) are typically manufactured in the form of dies on a wafer of semiconductor material. Particularly, after the manufacturing operations, the semiconductor material wafer is subdivided into dies, each one including a respective IC.
Before being packaged and sent to customers, and before being installed in complex electronic systems, the ICs are tested for evaluating their functionality, and particularly for assuring that they are not defective. During the test, information may be retrieved regarding global or local physical faults (such as, for example, the presence of undesired short circuits and breaks) and more generally regarding the IC operation on each tested die (for example, checking the waveforms of one or more output signals generated by the IC on each tested die). In this way, the subsequent phases of the manufacturing process (such as for example the linking of the bond wires, the packaging, and the final test) may be carried out only by the dies which have met predetermined results.
According to a known test technique, the dies including the ICs are tested before the semiconductor material wafer is subdivided. A test performed at wafer-level is denoted “wafer sort” or Electrical Wafer Sort (EWS).
In order to perform the test, a test apparatus is employed, which comprises a tester coupled to the semiconductor material wafer including the dies to be tested by means of a proper probe card.
The tester is adapted to manage signals to be used for performing the test; in the following, such signals will be denoted “test signals”. The test signals include test stimula (such as, commands, memory location addresses, data to be written in the memory device) generated by the tester and sent to each die to be tested through the probe card, and test response signals, which are generated by the ICs integrated in each die during the test phase in response to the received test stimula. The test response signals are sent by the IC integrated in each die to the tester through the probe card; such signals are then processed by the tester in order to obtain an indication regarding the correct (or incorrect) operation of the ICs integrated in the dies.
In order to allow the exchange of the test signals, the probe card is electrically coupled to the dies by means of particular probes. Particularly, the probe card consists of a Printed Circuit Board (PCB) connected to a plurality of mechanical probes adapted to physically contact input/output contact pads included in the die to be tested.
Each input/output contact pad is formed by an enlarged metallization region surrounded and possibly partially covered by a passivation layer.
During the test operations, the contact pad is etched or scratched by the mechanical action exerted by the probe's tip to establish a good electrical connection. In this way, it is possible to allow the test signals to be exchanged between the tester and the die to be tested.
A first category of known probe card comprises the probe cards provided with so-called cantilever probes. Such probes comprise a ring (for example, made of aluminum, special alloys, or ceramic material) which is connected to an epossidic support. Such epossidic support is adapted to support a plurality of test elements comprising elastic cantilever probes, formed by an alloy having good electrical and mechanical properties. Particularly, each cantilever probe includes a beam having a first end connected to the epossidic support and a second end including a tip, which in use it is intended to be forced against a contact pad of the die including the IC to be tested.
As an alternative to the probe cards including cantilever probes, it is possible to provide substantially vertical probes comprising conductive wires which pass through holes formed in a head of the probe card. In detail, the head of the probe card includes an upper guide plate stacked on a lower guide plate. Each probe has a tip that protrudes from the lower guide plate and it is adapted to electrically contact the corresponding contact pad of the die to be tested. A contact interface known as “space transformer” is connected to the upper guide plate and is adapted to electrically couple the probes to the printed circuit board in such a way to allow the signal exchange between the tester and the die to be tested.
A further type of probe card provides for the use of probes of the microelectromechanical type (known as MicroElectroMechanical System probes, or MEMS probes). With the term of MEMS probe it is intended a probe that has been manufactured through lithographic processes similar to those used for manufacturing the ICs. Thanks to the use of such lithographic processes, it is possible to manufacture a great number of MEMS probes having sufficiently homogeneous structural and electrical features in a manner that is relatively cheap.
Among the various known topologies of MEMS probes for the use in the integrated-circuits probe card field, one of the most widespread is formed by an elastic metallic beam having an end that is connected to a substrate (for example, made of a semiconductor or ceramic material) by means of one or more conductive-material support pillars, and the other end to a protruding tip adapted to electrically contact the contact pads of the die to be tested. The substrate is provided with proper conductive tracks connected to the support pillars. In this way, the exchange of test signals between the generic die and the tester by means of a MEMS probe may be carried out through a conductive path comprising the tip, the elastic beam, the support pillars and the conductive tracks formed in the substrate.
Further equivalent types of MEMS probes are known such as for example probes formed by a single metallic beam properly shaped which is directly connected to the substrate, probes formed by a stringy elastic element connected to the substrate and provided with a laminar tip, probes comprising silicon beams, and probes formed by thin curved foils of a conductive material.
If the ICs formed on the semiconductor material wafer comprise circuits intended to be exploited at the Radio Frequencies—in jargon, RF circuits—the testing provides for the use of Radio Frequency test signals—briefly, RF signals. For this purpose, the tester is capable of generating and acquiring RF signals, and the probe card is capable of providing and retrieving such RF signals to/from the ICs to be tested through the probes.
However, it is known that the management of RF signals may be critical, and may require one to employ a higher level of care with respect to that required for managing more slowly varying signals, i.e., low-frequency signals. Indeed, considering the generic conductive path of the probe card adapted to convey test signals from the tester to the probes contacting the ICs to be tested (and vice versa), such path, in the case of relatively low frequency test signals, may be assimilated to a short circuit, while, in the case of RF test signals, the same conductive path may behave as a transmission line. Consequently, in order to test RF circuits, one accurately designs the probe card, taking into account all the electromagnetic issues due to the presence of the transmission lines. For example, the probe cards presently employed for testing ICs by means of RF test signals comprise a plurality of proper expedients, such as coaxial cables and connectors, wide ground planes for the electromagnetic shielding, and so on.
However, although such solutions may be capable of efficiently shielding the transmission lines formed on the probe card, the correct carrying out of the test operations may not reach a successful conclusion because of the crosstalk phenomena that would occur between the probes connected to the probe card. Particularly, each probe, when in the path of an RF signal, behaves as an antenna irradiating electromagnetic waves in the surrounding area; such irradiated electromagnetic field may be picked up by the near probes of the probe card, negatively interfering with the successful conclusion of the test operations.
Among the solutions presently employed for resolving such problem, it is known to reduce the effects due to the crosstalk phenomenon by means of a proper design of the probes (regardless of the type) to diminish the irradiated electromagnetic field. For example, according to a known solution the electromagnetic field irradiated by a probe is reduced by diminishing as much as possible the length of the probe itself; however, by employing a solution of such type, it is possible to incur in drawbacks of other types, since a probe card equipped with probes that are too short may cause problems during the portion of the test phase which provides for the alignment of the probes to the pads of the IC to be tested.
In view of the above, when ICs formed on a semiconductor material wafer are to be tested by means of RF test signals, presently it may be preferred to test a single IC at a time, so as to avoid the arise of crosstalk phenomena among probes directed to contact different ICs. However, employing a solution of such type jeopardizes the possibility of testing more than one IC at the same time, consequently increasing the cost of the test operations in a non-negligible way compared to parallel testing.